1. Technical Field
Embodiments of the invention relate generally to scan testing in a System-on-a-Chip (SoC) or SoC-like design, and more particularly to a test architecture and method of applying decoupled clocking in scan testing.
2. Description of Related Art
System-on-a-Chip (SoC), a design style in which multiple cores such as processors and memories are integrated on a single piece of silicon, is currently widely used. Design efforts for a SoC can be greatly reduced by employing reusable Intellectual Property (IP) cores. However, manufacturing test and debug of such designs is difficult because different IP cores often employ different scan methodologies, e.g., different scan cell designs, different scan system architectures, and/or different clocking styles.
To test a core, many scan methodologies require an external test equipment to be able to directly control a scan clock of a core under test, to send and receive scan chain data synchronously with that scan clock, and to directly control the core's functional clock to disable it while the scan chain is shifting and to enable it while applying the scan test to the core logic. However, it is costly to add global routing between each core and pins of the chip, and/or to add pins to the chip exclusively for test. Therefore, it is common for all cores to share a test access mechanism and to re-use a set of functional mode pins. Due to the different clock styles and frequencies of the scan chains, of the cores, of the interconnect between the cores, and of the functional mode of the pins, sharing and re-use of pins are very difficult and lead to a very complex test interface design.